# University of Illinois Cracks Thermal Challenge for 3D Chips
Researchers at the University of Illinois have demonstrated a practical path forward for stacking silicon circuits vertically—a critical breakthrough as traditional transistor miniaturization hits fundamental physics limits.
The team, led by Associate Professor Qing Cao, successfully built three layers of silicon circuitry, each containing 625 transistors, while staying within the strict thermal constraints that have long blocked this approach. Standard device fabrication requires extreme heat (around 1,000°C), but upper layers must remain below 400°C to preserve metal connections.
Their solution uses ultrathin silicon membranes—just 10 nanometers thick—transferred onto existing circuits using a roll laminator at only 200°C. The resulting transistors achieved exceptional yields (98–100%) and performance comparable to conventional devices.
By stacking circuits vertically rather than simply shrinking them, chipmakers can dramatically increase computing density and reduce power consumption—particularly valuable for AI applications. The team has now prepared to scale this technology for industrial production.
Read the full article at [The Quantum Insider](https://thequantuminsider.com/2026/06/01/university-of-illinois-advances-monolithic-3d-chip-design/).